Flash memory devices have found increasing use in all manners of electronic products. For example, flash memory devices are used in digital cameras, personal digital assistants (PDAs) and cellular telephones, to name just a few products. A cross-section of a portion of a flash memory device is depicted in prior art FIG. 1. The figure represents an idealized conventional floating gate structure. The floating gate structure includes a substrate 10 and shallow trench isolation regions 12 formed in the substrate 10. A first polysilicon layer 14 is formed over the substrate 10 and the shallow trench isolation regions 12. An oxide-nitride-oxide (ONO) layer 16 is formed over the STI regions 12 and the first polysilicon layer 14. A second polysilicon layer 18 is conformally deposited over the ONO layer 16.
The first polysilicon layer 14 is formed on the STI regions 12 with narrow spacings. The second polysilicon layer 18 fills the gap in the narrow space to form the floating gate structure. Referring now to FIG. 2, as the geometry of the floating gate structures becomes smaller, a mis-alignment margin for the first polysilicon layer becomes much smaller. The mis-alignment increases the chances that the second polysilicon layer 18 will contact the corner of the STI region 12, as indicated at reference numeral 20 in FIG. 2. Some of the problems created by the close contact of the second polysilicon layer 18 with the corner of the STI region 12 include decreased endurance, reduced gate breakdown voltage, and a potential weak spot for gate leakage concerns. With the push for continuously shrinking geometries and the limitations of lithography printing alignment margins, it is desirable to provide a flash memory device that overcomes the concerns potentially created by mis-alignment.